1. Field of the Invention
The present invention is related to an active matrix display device formed on a plastic substrate and a method of fabricating the same, and more particularly, to a method of fabricating a thin film transistor including a multilayered gate electrode and an active matrix display device including the thin film transistor.
The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2005-S070-02, Flexible Display] in Korea.
2. Discussion of Related Art
FIG. 1 is a side cross-sectional view of a conventional active matrix display device.
Referring to FIG. 1, the conventional active matrix display device 100 includes a thin film transistor (TFT) formed on a glass substrate 110, and a capacitor and an organic light emitting diode (OLED) which are electrically connected to the TFT.
The TFT constituting the active matrix display device 100 includes a buffer insulating layer 120 formed on the glass substrate 110, an active layer 130 formed on the buffer insulating layer 120 and having source and drain regions 132 and a channel region 131, a gate insulating layer 140 formed on the active layer 130, a gate electrode 150 formed on the gate insulating layer 140, an interlayer dielectric 160 formed on the gate electrode 150, and source and drain electrodes 170 in contact with the source and drain regions 132 through a contact hole 161 formed on the interlayer dielectric 160.
When the active matrix display device 100 is fabricated on the glass substrate 110, in particular, when the TFT is fabricated, the doping profile of the active region 131 of the active layer 130 can be adjusted using lithography equipment to form a lightly doped drain (LDD).
However, when the active matrix display device is formed of a plastic substrate, the plastic substrate, unlike the glass substrate, is apt to be thermally deformed, so that metal of a gate metal layer is broken by stress due to a post annealing process when the relatively thick gate metal layer is deposited on the plastic substrate. When several layers need to be aligned in consideration of the thermal deformation of the plastic substrate, overlay accuracy becomes severely worse so that it is difficult to form an LDD without using a self-alignment process.
Further, according to a structure generated by etching of both sides of the gate metal and dopant diffusion due to subsequent laser activation for forming the self-aligned LDD on the plastic substrate (see “Fabrication of Low-Temperature Poly-Si Thin Film Transistor with Self-Aligned Graded Lightly Doped Drain Structure,” Electrochemical and Solid-State Letters, Huang-Chung Cheng), it is difficult to adjust the doping profile, and not only a leakage current but also a driving current is decreased.
Depositing thin amorphous silicon on polysilicon to form a dual active structure (see “Performance improvement of polycrystalline thin film transistor by adopting a very thin amorphous silicon buffer,” J. Non-Crystalline Solids, Kyung Wook Kim) requires a gate dielectric of high quality to be formed and amorphous silicon of good quality to be formed at a low temperature.